The present invention generally relates to the lithographic patterning of a semiconductor wafer. In particular, the present invention relates to a method and apparatus for conducting electrical performance testing of structures formed on the semiconductor wafer, and utilizing the results of the testing to efficiently predict critical dimension variations at various locations across a stepper field.
Errors may be introduced through various components and at various times in the manufacturing cycle of a wafer that contains several integrated circuits on respective circuit die. See the background below for further description of an exemplary manufacturing cycle. For example, during transfer of a pattern from the mask to the wafer, lens aberrations are known to cause distortions in structures formed from different areas of the same lens. Additionally, errors may be introduced during various developing and etching steps and/or through various other processes and components used during the manufacture a final production wafer.
In order to measure critical dimensions (CDs) of structures formed on a wafer so as to determine whether errors have occurred, it is known to use an electrical line width measurement technique. Electrical line width measurement involves measuring the resistivity of structures formed on a wafer using a probe and calculating CD""s of the structures based on the measured resistivity.
One higher precision measurement tool utilized to measure CDs and determine if defects are present with respect to structures formed on a wafer is a scanning electron microscope (SEM). An SEM is used to inspect structures at high magnification (e.g. on the order of 200xc3x97 to 2000xc3x97) using an electron beam in order to observe, for example, the line width or other dimension of each structure and/or to detect defects. While SEM provides higher resolution than the electrical line width measurement technique, at the sub-quarter micron level at which many wafer structures are currently being formed, SEM has also been found to have reached its resolution threshold. In addition, as the device density of wafers continues to increase, the process of utilizing SEM to analyze the large number of structures formed on each wafer is extremely time consuming given the need to accurately position and focus the SEM for each measurement.
One prior technique for testing a wafer has been to form a test structure on the wafer between adjacent integrated circuit die, e.g., in the xe2x80x9cscribe spacexe2x80x9d where the wafer eventually will be cut to separate respective integrated circuit die. Those test structures have been tested by the various prior techniques mentioned above. The test data obtained, though, does not necessarily represent conditions, e.g., critical dimensions (CD""s) of structures over parts of the wafer that are not at or near the test structure. Thus there is a need to improve the ability to represent CD""s over large areas, and even over the entire surface, of a wafer.
Also, line width variations may cause proportional changes in operation or response for some devices of an integrated circuit structure on an integrated circuit die and non-proportional changes in other integrated circuit structures on the die. There is a need to improve the accuracy of data representing such variations and the utilization of data representing such variations.
Referring initially to FIG. 1a, integrated circuits are formed on semiconductor wafers 10 typically made from silicon. The wafers 10 are substantially round and typically have a diameter of approximately 15 to 20 cm. Each wafer 10 is divided up into individual circuit die 15 which contain an integrated circuit. Since a single integrated circuit die 15 is often no more than 1 cm2, a great many integrated circuit die 15 can be formed on a single wafer 10. After the wafer 10 has been processed to form a number of integrated circuit die on its surface, the wafer 10 is cut along scribe lines 20 to separate the integrated circuit die for subsequent packaging and use.
Formation of each integrated circuit die on the wafer is accomplished using photo-lithography. In general, lithography refers to processes for pattern transfer between various media. The basic photo-lithography system consists of a light source, a photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the photomask.
Referring to FIG. 1b, during an intermediate stage in the manufacturing cycle, the wafer 10 is shown to include a film 25 which overlies the wafer 10 and a resist 30 disposed on the film 25. Exposing the resist 30 to light or radiation of an appropriate wavelength through the photomask causes modifications in the molecular structure of the resist polymers to allow for transfer of the pattern from the photomask to the resist 30. The modification to the molecular structure allows a resist developer to dissolve and remove the resist in exposed areas, presuming a positive resist is used. If a negative resist is used, the developer removes the resist in the unexposed areas.
Referring to FIG. 1c, once the resist 30 on the wafer has been developed, one or more etching steps take place which ultimately allow for transferring the desired pattern to the film 25 and/or wafer 10. For example, in order to etch the film 25 disposed between the resist 30 and the wafer 10, a wet or dry etchant is applied over the patterned resist 30. The etchant comes into contact with the underlying film layer by passing through openings 35 in the resist formed during the resist exposure and development steps. Thus, the etchant serves to etch away those regions of the film layer which correspond to the openings in the resist, thereby effectively transferring the pattern in the resist to the film layer as illustrated in FIG. 1d. In subsequent steps, the resist is removed and another etchant may be applied over the patterned film layer to transfer the pattern to the wafer or to another layer in a similar manner.
Presently, there are a variety of known techniques for transferring a pattern to a wafer using photolithography. For instance, referring to FIG. 2, a reduction step-and-repeat system 50 (also called a reduction stepper system 50) is depicted. The reduction stepper system 50 uses refractive optics to project a mask image onto a resist layer 30. The reduction stepper system 50 includes a mirror 55, a light source 60, a filter 65, a condenser lens system 70, a mask 75, a reduction lens system 80, and the wafer 10. The mirror 55 behaves as a collecting optics system to direct as much of the light from the light source 60 (e.g. KrF laser, ArF laser, mercury-vapor lamp, etc.) to the wafer 10. The filter 65 is used to limit the light exposure wavelengths to the specified frequencies and bandwidth. The condenser system 70 focuses the radiation through the mask 75 and to the reduction lens system 80 to thereby focus a xe2x80x9cmaskedxe2x80x9d radiation exposure onto one of the circuit die 15.
Since it is complex and expensive to produce a lens capable of projecting a mask of an entire wafer, the reduction stepper system 50, projects an image only onto a portion of the wafer 10 corresponding to one or more individual circuit die 15. This image is then stepped and repeated across the wafer 10 in order to transfer the pattern to the entire wafer 10 (e.g. across the entire xe2x80x9cstepper fieldxe2x80x9d). Consequently, the size of the wafer is no longer a consideration for the system optics.
Current reduction stepper systems 50 utilize masks that contain a pattern that is an enlargement of the desired image on the wafer 10. Consequently, the mask pattern is reduced when projected onto the resist 30 during exposure (and thus the name xe2x80x9creduction stepperxe2x80x9d).
With an ever increasing number of integrated circuit patterns being formed on a circuit die, the importance of properly designing patterns to form structures that are isolated and non-interfering with one another has also increased. Accordingly, when designing a pattern to place on a mask, it is of significant benefit to know in advance the amount of error to expect with respect to the corresponding structures formed on the wafer so that such error can be accounted for in advance. Errors are known to affect, for example, the line width, length, and position of structures or features formed on each circuit die.
Accordingly, there is a strong need in the art for a method and apparatus of efficiently and reliably determining CD variations occurring in structures formed on a wafer.
There also is a need to improve sensitivity of detecting or measuring CD variations.
There is a need, too, to make the data obtained by such detecting or measuring more relevant and useful.
Briefly, according to an aspect of the invention test structures distributed over the entire wafer field of a wafer that is used as a test wafer are used to obtain data on CD""s.
According to another aspect, a test wafer is made using a method of making a usual wafer, the test wafer having test structure representing characteristics that would be included in such usual wafer, the test wafer being for testing and testing being carried out to check CD""s, and the data representative of such CD""s for use in characterizing the wafer, integrated circuit die thereof, and/or the manufacturing process of making such wafer.
According to another aspect, a wafer of a size that typically provides a number of integrated circuit die has test structures distributed thereover and is used as a test wafer to obtain CD data.
According to another aspect an entire test wafer is used for device measurement to obtain information regarding stepper device and/or other wafer manufacturing accuracy and/or to obtain wafer accuracy; and the obtained data may be used in conjunction with the manufacturing of subsequent wafers.
The inventors of the present invention have found that a correlation can be identified between the electrical performance of device structures formed on a wafer and CD variations occurring among the device structures formed across a stepper field. For example, it has been observed that variations in CD can be predicted by observing and comparing the processing speed of two or more of the same device structures formed at different positions in the stepper field. Accordingly, by performing parametric testing of device structures formed at various locations in the stepper field, it is possible to quickly analyze and predict the amount of CD variations which will occur during a lithographic process. The outcome of the analysis may then be used, for example, to adjust one or more characteristics of a lens to account for predicted CD variations. It has been found that utilizing the present invention, reliable CD predictions are obtainable for structures sized below a quarter-micron line width.
In accordance with one embodiment of the present invention, a test wafer is produced to include an array of test structures formed across a stepper field. The test structures are preferably structures which are commonly found in a microprocessor or other device to be formed on a final production wafer. For example, the test structures may include transistors, ring oscillators, resistors, diodes, etc. In this manner, the test structures on the test wafer may be used to more accurately predict the actual CD variations which are likely to occur with respect to device structures used in the final production wafer.
According to one feature of the present invention, each of the test structures formed across the stepper field is the same test structure so that a comparison of the electrical performance of each of the test structures can be readily obtained and analyzed to predict CD variations. Once formed, the test structures are subjected to parametric testing using known testing procedures in the art. In one embodiment of the present invention, parametric testing includes testing the processing speed of each of the test structures. Additionally, parametric testing may include the measuring of the drive current, off-state current, and other electrical parameters of each test structure.
Once one or more desired parameters of the test structures are measured, the data collected is compared with predetermined performance data. The predetermined performance data may be known optimum performance data corresponding to the performance characteristics obtainable by a test structure which is not subjected to CD variations. Alternatively, the data collected may be used to compare performance data among the various test structures formed on the wafer itself thereby providing an indication of a relative difference in CD variation occurring at different locations.
For example, if one of the desired parameters is processing speed, then the measured processing speed of each test structure may be compared with an optimal processing speed realizable if there were no CD variations in the test structure and the test structure being of a nominal value, e.g. having transistors of the same size. Next, a change in performance variation (xcex94pv) is calculated and compared with values in a CD conversion chart to convert the xcex94pv to a predicted CD variation. The values stored in the CD conversion chart may be predetermined from prior testing and/or though performing computer simulations using known simulation packages in the art such as S.P.I.C.E. which predicts performance variation as a function of the CD. Finally, the predicted CD variations are stored in a memory of an analysis tool, computer, or other device and a report is provided or made available to a user showing the predicted CD variations throughout the stepper field.
Once obtained, the predicted CD variations on the test wafer may be used to adjust lens characteristics, reticle patterning, or other aspects of the photolithographic transfer process to account for the predicted CD variations.
According to one aspect of the present invention, a method of estimating an amount of critical dimension (CD) variation to expect at a selected point on a semiconductor wafer following a photolithographic pattern transfer process is provided. The method includes the steps of forming a test structure at the selected point on the wafer during the photolithographic pattern transfer process, measuring at least one electrical performance value of the test structure, and estimating the amount of critical dimension variation to expect based on the measured at least one electrical performance value.
In accordance with another aspect of the present invention, a method of estimating an amount of critical dimension variation to expect across a wafer following a photolithographic pattern transfer process is provided. The method includes the steps of forming a plurality of test structures at predetermined locations on the wafer during the photolithographic pattern transfer process, measuring at least one electrical performance value of at least a portion of the plurality of test structures, and estimating the amount of critical dimension variation to expect based on the measured at least one electrical performance value of the at least a portion of the plurality of test structures.
In accordance with yet another aspect of the present invention, a system for estimating an amount of critical dimension variation to expect at various locations across a surface of a wafer following patterning of a semiconductor wafer using photolithography is provided. The system includes means for forming a plurality of test structures on the wafer, means for measuring electrical performance characteristics of at least a portion of the plurality of test structures, and means for correlating the electrical performance characteristics of the at least a portion of the plurality of test structures to critical dimension variations for each of the at least a portion of the plurality of test structures.
In accordance with still another aspect of the present invention, a device for estimating critical dimension variations across a stepper field is provided. The device including a processor, a memory coupled to the processor, a data input device coupled to the processor for receiving electrical performance characteristics of a plurality of test structures formed on a semiconductor wafer, wherein the memory includes a table for correlating the electrical performance characteristics with an estimated critical dimension variation.
To the accomplishment of the foregoing and related ends, the invention then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set fourth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such embodiments and their equivalents. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.